Most of the known wafer top near edge inspection and metrology systems utilize propriety, dedicated scanning stage (usually R/T type) and a camera located at approximate known location of the wafer edge.
FIG. 1 illustrates a prior art chuck 10. The chuck 10 has an upper surface that is made of a non-reflective material and does not provide a proper contrast to the edge of a wafer that is placed on the chuck. FIG. 1 illustrates the chuck as including as array of vacuum openings and a recess 12 for receiving a wafer interface.
FIG. 2 illustrates a cross sectional view of a prior art wafer 20. While FIG. 2 illustrates a relatively ordered wafer edge that includes linear surfaces—in practice the edge surface is usually deformed. FIG. 2 illustrates an edge surface 21, top bevel surface 22, low bevel surface 23, upper and lower surfaces 24 and 25 as well as two layers 28 and 29 that are positioned above each other and have different reflective indexes. The first layer 28 can be relatively bright while the second layer 29 can be relatively dark.
Most of the inspection systems are dedicated for wafer edge inspection only.
Other wafer inspection and metrology systems are mainly intended for patterned wafer area inspection—an area with a well defined periodic pattern (field/dice). The inspection area and an applicable algorithm is explicitly defined by user with respect to single field/die geometry and then repetitively applied to all existing fields/dice.
The partial pattern and additionally or alternatively, un-patterned wafer edge areas do not exhibit previously mentioned geometry.
Therefore, the patterned wafer area inspection system and methods (algorithms) can not be applied per se to the wafer edge due to the undefined geometry of the edge. Moreover, since the wafer edge geometry varies for each wafer, the mentioned geometry can not be trained.
Most of the wafer inspection systems are using dedicated pre-aligning systems to define wafer notch/flat orientation. Pre-aligning systems, mostly integrated with wafer handling robotics are time consuming with respect to overall wafer inspection cycle.